Implementing synchronous triggers for waveform capture in an FPGA prototyping system

ABSTRACT

An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.

FIELD

The present patent document relates generally to functional verificationsystems for circuit designs. In particular, the present patent documentrelates to a method and apparatus for implementing synchronous triggersfor waveform capture in a multiple FPGA system.

BACKGROUND

Designers of integrated circuit devices (“chips”), generallyapplication-specific integrated circuits (“ASICs”), use prototyping aspart of the electronic design automation process prior to manufacture ofthe chip. Prototyping is one type of hardware-based functionalverification that allows the circuit designer to observe the behavior ofthe circuit design under conditions approximating its final,manufactured performance. During prototyping, a circuit design,generally written in register transfer language (“RTL”) code, isprogrammed into one or more programmable logic chips, frequentlyfield-programmable gate arrays (“FPGA”) on a prototyping board.FPGA-based prototypes are a fully functional representation of thecircuit design, its circuit board, and its input/output (“I/O”) devices.Also, FPGA prototypes generally run at speeds much closer to the clockspeed at which the manufactured chip will run than other types offunctional verification, e.g., software simulation, thereby allowing forverifying the circuit design under many more conditions in the sameamount of time than other verification methods, and in particular,software simulation. The circuit design prototype may also be operatedin another electronic circuit, e.g., the electronic circuit for whichthe design under verification will be used after fabrication, so thatthe circuit design prototype may be observed and tested in anenvironment in which the manufactured chip will be used. As such,circuit designers may use FPGA prototyping as a vehicle for softwareco-development and validation, increasing the speed and accuracy ofsystem developments.

Prototyping of a circuit design using programmable logic chips (e.g.,FPGAs) can have advantages over other types of functional verification,namely emulation using a plurality of emulation processors. First,prototyping using programmable logic chips generally results in higherspeed relative to emulation using emulation processors. Second, suchhigher-speed circuit design prototypes using programmable logic chipscan sometimes even run in real-time, that is, the prototype may run atthe intended clock speed of the manufactured chip, rather than a reducedclock speed. This is not always the case, notably for higher performancecircuit designs that have clock speeds higher than the maximum allowedby the programmable logic chips. Third, such prototyping systems usingprogrammable logic chips are generally of lower cost than an emulationsystem using processors.

Exemplary hardware used in prototyping comprises FPGAs or other types ofprogrammable logic chips, input/output circuitry, and interconnectcircuitry connecting the programmable logic chips to each other and tothe input-output circuitry. An example of commercial prototypinghardware includes the DN7006K1 OPCIe-8T manufactured by the DINI Groupof La Jolla, Calif. The DN7006K10PCIe-8T features six Altera Stratix 33SL340 (FF1760) FPGAs, a configuration FPGA, global clock generationhardware, interconnect connecting the FPGAs to each other, input/outputdevices including an eight lane PCI Express Endpoint, and DDR SODIMMslots for the insertion of RAM.

To enable a circuit designer to evaluate the circuit design prototype,FPGAs are generally embedded with an internal logic analyzer circuitthat can capture and store logic signals during operation. Each internallogic analyzer can be triggered on a combination of multiple signalsfrom the user logic. Once these signals are captured, the internal logicanalyzer can unload the data through an interface to a computer.Typically, an interface is connected between the computer and the FPGAwhere the computer can arm the internal logic analyzer and poll it untila data acquisition has been made. While internal logic analyzers workwell for debugging logic of each individual FPGA, existing designs havelimitations for multiple FPGA systems. Specifically, each logic analyzercaptures data waveforms for its respective FPGA independently of theother FPGAs in the system. This design limitation leads to confusion andloss of correct and efficient debugging for circuit design prototypesthat include multiple FPGAs.

SUMMARY

Accordingly, an apparatus and method is disclosed to implementsynchronous triggers for waveform capture in a multiple FPGA system. Thedisclosed apparatus and method enable internal logic analyzers of eachFPGA to synchronously capture waveforms from the device when it isoperating and under the actual conditions that might produce amalfunction of the circuit design prototype.

According to an embodiment, an apparatus is provided for synchronizingtriggers for waveform capture of a circuit design in a prototypingsystem. The apparatus comprises trigger net circuitry including at leastone trigger net and an output and a plurality of programmable logicdevices. Each programmable device includes logic circuitry programmableto correspond to the circuit design; a logic analyzer circuit includingat least one logic connection coupled to the logic circuitry formonitoring operating signals of the circuit design; and a registerhaving a data input coupled to the output of the trigger net circuitryand an output coupled to a control input of the logic analyzer circuit.

According to an embodiment, one or more of the plurality of programmablelogic devices of the apparatus includes the trigger net circuitry.

According to an embodiment, each of the plurality of programmable logicdevices of the apparatus is a field-programmable gate array.

According to an embodiment, the trigger net circuitry of the apparatusincludes at least one multiplexer with a select input coupled to a hostinterface of the prototyping system.

According to an embodiment, the host interface is configured to controlthe trigger net circuitry to potentially output a high logic signal.

According to an embodiment, each register of the plurality ofprogrammable logic devices synchronously outputs a control logic signalto the respective logic analyzer circuit coupled thereto.

According to an embodiment, each logic analyzer circuit of the pluralityof programmable logic devices synchronously captures a waveform from thelogic circuitry of the respective programmable logic device.

According to an embodiment, each logic analyzer circuit of the pluralityof programmable logic devices is programmed to synchronously capture awaveform from the logic circuitry of the respective programmable logicdevice via the at least one logic connection.

According to an embodiment, a computer-implemented method is providedfor synchronizing triggers for waveform capture of a prototyping system.The method includes partitioning a circuit design for programming into aplurality of programmable logic devices; programming one or more of theplurality of programmable logic devices to include trigger netcircuitry, the trigger net circuitry including at least one trigger netand an output; programming an input of one register in each of theplurality of programmable logic devices to receive a control signal fromthe output of the trigger net circuitry; and programming an output ofthe one register in each of the plurality of programmable logic devicesto transmit a trigger signal to a logic analyzer circuit in therespective programmable logic device.

According to an embodiment, the method includes programming at least onelogic connection of each logic analyzer circuit to receive at least oneoperating signal from logic circuitry of the respective programmablelogic device.

According to an embodiment, the method includes connecting a hostinterface of the prototyping system to an input of the trigger netcircuitry.

According to an embodiment, the method includes transmitting a controlsignal on the host interface to the trigger net circuitry to potentiallyoutput a high logic signal.

According to an embodiment, the method includes synchronously outputtinga control logic signal by each register of the plurality of programmablelogic devices to the respective logic analyzer circuit coupled thereto.

According to an embodiment, the method includes synchronously capturing,by each respective logic analyzer circuit, a waveform from the logiccircuitry of the respective programmable logic device.

According to an embodiment, a computer-readable non-transitory storagemedium is provided having stored thereon a plurality of instructions,the plurality of instructions when executed by a computer, cause thecomputer to partition a circuit design for programming into a pluralityof programmable logic devices; program one or more of the plurality ofprogrammable logic devices to include trigger net circuitry, the triggernet circuitry including at least one trigger net and an output; programan input of one register in each of the plurality of programmable logicdevices to receive a control signal from the output of the trigger netcircuitry; and program an output of the one register in each of theplurality of programmable logic devices to transmit a trigger signal toa logic analyzer circuit in the respective programmable logic device.

According to an embodiment, the plurality of instructions when executedby a computer further cause the computer to program at least one logicconnection of each logic analyzer circuit to receive at least oneoperating signal from logic circuitry of the respective programmablelogic device.

According to an embodiment, the plurality of instructions when executedby a computer further cause the computer to connect a host interface ofthe prototyping system to an input of the trigger net circuitry.

According to an embodiment, the plurality of instructions when executedby a computer further cause the computer to transmit a control signal onthe host interface to the trigger net circuitry to potentially output ahigh logic signal.

According to an embodiment, the plurality of instructions when executedby a computer further can cause the computer to program each register ofthe plurality of programmable logic devices to synchronously output acontrol logic signal to the respective logic analyzer circuit coupledthereto.

According to an embodiment, the plurality of instructions when executedby a computer further cause the computer to synchronously capture, byeach respective logic analyzer circuit, a waveform from the logiccircuitry of the respective programmable logic device.

The above and other preferred features described herein, includingvarious novel details of implementation and combination of elements,will now be more particularly described with reference to theaccompanying drawings and pointed out in the claims. It will beunderstood that the particular methods and apparatuses are shown by wayof illustration only and not as limitations of the claims. As will beunderstood by those skilled in the art, the principles and features ofthe teachings herein may be employed in various and numerous embodimentswithout departing from the scope of the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included as part of the presentspecification, illustrate the presently preferred embodiments andtogether with the general description given above and the detaileddescription of the preferred embodiments given below serve to explainand teach the principles described herein.

FIG. 1 illustrates an exemplary circuit design partitioned into blocksof circuitry, each configured to synchronously capture data according toan exemplary embodiment.

FIG. 2 illustrates a flow diagram of a method for implementingsynchronous triggers for waveform capture in a multiple FPGA system.

FIG. 3 illustrates a software flow chart for a method for programmingthe trigger net logic into FPGAs for the prototyping design according toan exemplary embodiment.

The figures are not necessarily drawn to scale and the elements ofsimilar structures or functions are generally represented by likereference numerals for illustrative purposes throughout the figures. Thefigures are only intended to facilitate the description of the variousembodiments described herein; the figures do not describe every aspectof the teachings disclosed herein and do not limit the scope of theclaims.

DETAILED DESCRIPTION

Each of the features and teachings disclosed herein can be utilizedseparately or in conjunction with other features and teachings.Representative examples utilizing many of these additional features andteachings, both separately and in combination, are described in furtherdetail with reference to the attached drawings. This detaileddescription is merely intended to teach a person of skill in the artfurther details for practicing preferred aspects of the presentteachings and is not intended to limit the scope of the claims.Therefore, combinations of features disclosed in the following detaileddescription may not be necessary to practice the teachings in thebroadest sense, and are instead taught merely to describe particularlyrepresentative examples of the present teachings.

In the following description, for purposes of explanation only, specificnomenclature is set forth to provide a thorough understanding of thepresent invention. However, it will be apparent to one skilled in theart that these specific details are not required to practice the presentinvention.

Some portions of the detailed descriptions that follow are presented interms of algorithms and symbolic representations of operations on databits within a computer memory. These algorithmic descriptions andrepresentations are the means used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of steps leading to a desiredresult. The steps are those requiring physical manipulations of physicalquantities. Usually, though not necessarily, these quantities take theform of electrical or magnetic signals capable of being stored,transferred, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like. It should be borne in mind, however, thatall of these and similar terms are to be associated with the appropriatephysical quantities and are merely convenient labels applied to thesequantities. Unless specifically stated otherwise as apparent from thefollowing discussion, it is appreciated that throughout the description,discussions utilizing terms such as “processing” or “computing” or“calculating” or “determining” or the like, refer to the action andprocesses of a computer system, or similar electronic computing device,that manipulates and transforms data represented as physical(electronic) quantities within the computer system's registers andmemories into other data similarly represented as physical quantitieswithin the computer system memories or registers or other suchinformation storage, transmission or display devices.

The present patent document also relates to an apparatus for performingthe operations herein. This apparatus may be specially constructed forthe required purposes, or it may comprise a general-purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program may be stored in a computerreadable storage medium, such as, but is not limited to, any type ofdisk, including floppy disks, optical disks, CD-ROMs, andmagnetic-optical disks, read-only memories (ROMs), random accessmemories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any typeof media suitable for storing electronic instructions, and each coupledto a computer system bus.

The algorithms presented herein are not inherently related to anyparticular computer or other apparatus. Various general-purpose systemsmay be used with programs in accordance with the teachings herein, or itmay prove convenient to construct a more specialized apparatus toperform the required method steps. The required structure for a varietyof these systems will appear from the description below. It will beappreciated that a variety of programming languages may be used toimplement the teachings of the invention as described herein.

Moreover, the various features of the representative examples and thedependent claims may be combined in ways that are not specifically andexplicitly enumerated in order to provide additional useful embodimentsof the present teachings. It is also expressly noted that all valueranges or indications of groups of entities disclose every possibleintermediate value or intermediate entity for the purpose of originaldisclosure, as well as for the purpose of restricting the claimedsubject matter. It is also expressly noted that the dimensions and theshapes of the components shown in the figures are designed to help tounderstand how the present teachings are practiced, but not intended tolimit the dimensions and the shapes shown in the examples.

FIG. 1 illustrates an exemplary circuit design 100 partitioned intothree blocks of circuitry, each configured to synchronously capture dataaccording to an exemplary embodiment. As shown, each block is programmedinto one FPGA, shown as FPGA 110, 120 and 130, that are part of anexemplary prototyping system comprising a circuit board that hostsFPGAs, clock generation circuits, interconnect lines connecting theFPGAs to each other, clock generation circuitry, I/O devices forcommunication to external hardware, connectors, and memory. It should beappreciated that the programmable logic devices used in this embodimentare FPGAs. However, as will be appreciated by one of skill in the art,any number of programmable logic devices suitable for prototyping may beused in place of the FPGAs of the exemplary embodiment.

Partitioning of circuit design 100 may be accomplished using any numberof partitioning techniques well-known to those in the field ofprototyping. Each of FPGAs 110-130 may host additional circuitry formanagement, control, and testing functionality that includes internallogic analyzers. Although not shown, it should be appreciated that thecircuit design 100 includes signal interconnects between each of FPGAs110, 120 and 130 for the transmission and receipt of signals to and fromthe respective FPGAs. Such interconnects include pins of packagescontaining the FPGAs and conductors routed on the prototype circuitboard hosting the FPGAs.

Each of FPGAs 110-130 includes a plurality of registers or flip-flops.In the exemplary embodiment of FIG. 1, FPGAs 110-130 are each shown toinclude one register 112, 122, and 132 that is utilized by the exemplarysystem and method to serve as the synchronous trigger during testing ofthe circuit design prototype. In particular, each register 112, 122, and132 includes a data input D, a clock input CLK and a data output Q. Theoutput Q of each of these registers is coupled to an internal logicanalyzer 113, 123 and 133 on each of the FPGAs 110-130, respectively,with the output signal Q serving as a control signal or “trigger” signalthat triggers the respective internal logic analyzers 113, 123 and 133to begin capturing a waveform of data for its respective FPGA.

In addition, each FPGA 110, 120 and 130 includes user logic 114, 124 and134 and logical connections 115, 125 and 135 programmed into the FPGAs110, 120 and 130 communicatively coupled to the internal logic analyzers113, 123 and 133, respectively. As should be appreciated to thoseskilled in the art, the user logic can be programmable logic thatcorresponds to the actual circuit design being evaluated. Moreover, thelogical connections 115, 125 and 135 allows signals from user logic tobe transmitted to logic analyzer circuits 113, 123 and 133. Thesesignals can include a system clock, signals to monitor and the like. Thespecific signals to be monitored by the logic analyzer circuits can bespecified by the circuit designer. As should be further understood, thelogic analyzer circuits each can communicate with an external computerto transmit information including the current status of logic analyzercircuit and data captured from the FPGA. Connections between the logicanalyzer circuits and an external computer should be understood to oneskilled in the art and are not shown in FIG. 1.

The registers on the FPGAs can collectively be considered synchronizedflip flops such that the output Q will output a high logic signal (i.e.,a “1”) or a low logic signal (i.e., a “0”) at the same time as oneanother. Advantageously, by synchronizing the trigger signals, internallogic analyzers 113, 123 and 133 are controlled to capture waveformsfrom the user logic at precisely the same time for each FPGA in thecircuit design.

The synchronized trigger signal Q of each of the FPGA is controlledbased on a synchronized input signal to the data input D. In particular,each of the data inputs D are commonly connected to an output of an ORgate 116 in the FPGA 110. The OR gate 116 is part of control circuitrythat synchronously controls all of the logic analyzer circuits in eachof the respective FPGAs 110, 120 and 130. In the exemplary embodiment,the control circuitry is programmed on one or more of the FPGAs (shownas programmed on FPGAs 110, 120 and/or 130) and can be consideredtrigger net circuitry 10 in that it serves as control circuitry toinitiate the trigger for synchronous waveform capture by the FPGAs 110,120 and 130. Specifically, the OR gate 116 can output a control logicsignal, such as a high logic signal (i.e., a “1”), that is fed to thedata input D of each register 112, 122, and 132. The clock signal CLKcontrols the output of the registers 112, 122, and 132, such that thedata output Q will be driven to a “1” in response to the clock signalCLK. Alternatively, the OR gate 116 can output a low logic signal (i.e.,a “0”) that is is fed to the data input D of each register 112, 122, and132. The clock signal CLK controls the output of the registers 112, 122,and 132, such that the data output Q will be driven to a “0” in responseto the clock signal CLK.

It should be appreciated that this circuitry can be customized and/orcontrolled by the circuit designer. For example, in one embodiment, theinternal logic analyzers 113, 123 and 133 can be controlled to capturewaveforms when the OR gate 116 feeds a low logic signal. Furthermore, inthe exemplary embodiment, each internal logic analyzers 113, 123 and 133captures waveforms in response to the trigger signal and continues thedata capture until the core of the logic analyzer reaches its capacityfor data storage.

As further shown in FIG. 1, the OR gate 116 has two input pins that arecoupled to additional logic. In the exemplary embodiment, the additionallogic is programmed to define trigger net signals used to initiate thesynchronous waveform capture. As shown, the input pins of the OR gate116 are coupled to first and second multiplexers 118A and 118B, whicheach include two data input pins and a select input pin. Respectivefirst inputs of each of the multiplexers 118A, 118B are coupled tobuffers 119A and 119B whose input receives trigger net signals 1 and 2.These trigger net signals are part of the user logic defined by the userand are enabled and disabled through the multiplexer selection signals.It should be understood that when either multiplexers 118A ormultiplexers 118B outputs a high logic signal (i.e., a “1”), the outputof the OR gate 116 will be a “1”, which serves as the control signal forsynchronous trigger signals as discussed above. As further shown, theselect signal for the multiplexers 118A and 118B are preferably drivenby a connection to the host interface, which is shown as an NMB or mainbus coupled to the host interface. This connection enables controls thetrigger net signals to initiate the synchronous waveform capture by eachFPGA. It should be appreciated that the logic circuitry shown in FIG. 1to provide the trigger net signals for the synchronous waveform captureis an exemplary embodiment and that variation of this circuitry can beimplemented in alternative embodiments.

FIG. 2 illustrates a flow diagram of a method 200 for implementingsynchronous triggers for waveform capture in a multiple FPGA system.Initially, at step 205, a designer generates a circuit design forprototyping into an output file. A wide variety of electronic designautomation (“EDA”) tools can be used to generate and compile the circuitdesign. Once the circuit is designed, the user issues a compile commandat step 210 to compile the user's device design into the prototypecircuit design. The exemplary process for compiling the device design toinclude the trigger net logic 10 disclosed herein will be described indetail below with respect to FIG. 3. However, according to the exemplaryembodiment, it should generally be understood that step 210 includespartitioning the user's design onto FPGAs of the prototyping system andprogramming each FPGA to include at least one register (shown asregisters 112, 122 and 132 in the example shown in FIG. 1) used toprovide a trigger that is supplied as a control signal to a respectivelogic analyzer on each FPGA. In addition, programming of the circuitdesign includes defining and creating a trigger net to provide a controlsignal for each register of each partitioned FPGA as described abovewith respect to FIG. 1.

Once the circuit is designed and compiled, the circuit design prototypecan then be evaluated by synchronously capturing waveform data. Inparticular, at step 215, a host interface or bus is connected to thetrigger net logic 10 of the circuit design as discussed above withrespect to FIG. 1. In one embodiment of the invention, the hostinterface is connected to an input pin of one of the FPGA's (i.e., theFPGA with the trigger net logic 10) that has been specified by the userduring the circuit design of step 205.

Next, at step 220, the circuit designer begins execution of the systemin which the circuit design prototype is operating to begin the designevaluation and debugging process. During operation the circuit designercan then initiate the synchronous waveform capture of the FPGAs of thecircuit design by transmitting a control signal (step 225) on the hostinterface to the trigger net circuitry (i.e., the control circuitry) 10programmed on one of the FPGAs as discussed above. As described abovewith respect to FIG. 1, the trigger net control signal results inenabling of the trigger signals through the multiplexer which canpotentially result in a control logic signal (e.g., a high logic signal“1”) from OR gate 116 that is input to each of the registers 112, 122,and 132 of the respective FPGAs. This is shown as step 230 in FIG. 2. Atthe next clock cycle, the registers 112, 122, and 132 each output atrigger signal at step 235, which is sent to respective logic analyzers113, 123, and 133, with the trigger signals synchronously controllingthe analyzers to begin the desired waveform capture. It should beunderstood that the waveform capture for each FPGA begins at the sameinstant, which facilitates a more accurate debugging by the circuitdesigner as described above. Also, as described above, each internallogic analyzers 113, 123 and 133 captures waveforms in response to thetrigger signal and continues the data capture until the core of thelogic analyzer reaches its capacity for data storage.

Finally, once data capture is complete by each logic analyzer, theactual data capture by each logic analyzer can be uploaded over a serialinterface cable or the like to the circuit designer's host computer(step 240). The circuit designer is then able to graphically view thesesignals received from the logic analyzers, where the signals can bepresented in a waveform view annotated with the names of the signals orthe like.

FIG. 3 illustrates a software flow chart for a method 300 forprogramming the trigger net logic 10 into FPGAs for the prototypingdesign according to an exemplary embodiment. As described above, themethod shown in FIG. 3 corresponds to an exemplary embodiment of step210 of FIG. 2. Moreover, the prototyping software is run on aworkstation, comprising a general purpose processor, RAM, hard-disk orother permanent storage, and input/output devices in electricalcommunication with a prototyping board comprising FPGAs or otherprogrammable logic chips, input/output circuitry, and interconnectcircuitry connecting the programmable logic chips to each other and tothe input-output circuitry. In addition, the design file for the circuitdesign can be in any format suitable for partitioning and programminginto programmable logic chips of a prototyping system, for examplehardware description language (“HDL”) format.

Initially, at step 305, the trigger net logic circuitry 10 is programmedfor the circuit design, which can be the trigger net circuitry 10 shownin FIG. 1, for example. Next, at step 310, the circuit design ispartitioned into two or more partitions, each partition to be programmedinto a distinct FPGA of the prototyping board. As previously discussed,partitioning may be accomplished using any number of techniques wellknown in the field of prototyping that divide up the logic of thecircuit design for programming into a plurality of FPGAs. The softwarethen begins the loop containing steps 315-325 that generates the logicfor the synchronous triggers to be programmed into each FPGA hosting apartition. In particular, at decision 315, if each FPGA to be programmedwith a partition has already had a register programmed to provide thesynchronous control signal to the respective logic analyzer circuit,then the software proceeds to step 330, which is the end of the designprocess. If not every FPGA to be programmed with a partition has alreadybeen programmed with the circuitry, which should be the case the firsttime decision 315 is encountered by the software, the software proceedsto program the circuitry needed for synchronous waveform capture into afirst FPGA of the circuit design at step 320. In particular, step 320involves designating a register (e.g., register 112 of FIG. 1) in thefirst FPGA (e.g., FPGA 110 of FIG. 1) for the synchronous waveformcapture process. At step 325, the input net of the register 112 isconnected to the output of the trigger net (e.g., the output of OR gate116 of FIG. 1) and the output net of register 112 is connected to theinput of the logic analyzer of the FPGA, for example, logic analyzer 113of FPGA 110.

After step 330 is performed for the first FPGA of the circuit design,the method returns to step 315 to query whether every other FPGA hasbeen programmed to include the circuitry for the synchronous trigger forwaveform capture. If the answer is “NO”, steps 320 and 325 are performedfor the next FPGA in the circuit design. In the exemplary embodiment,this loop is repeated until each partitioned FPGA in the circuit designhas been programmed to include the circuitry for synchronous datawaveforms according to the exemplary embodiment. It should beappreciated that in an alternative embodiment, only some, but not all,of the FPGAs in the circuit design are programmed to include thesynchronous trigger of the exemplary embodiment. Once each desired FPGAof the circuit design is programmed according to steps 320 and 325, step315 will be answered YES and the method proceeds to step 330, which isthe end of the circuit design programming. At this point, the designfile is compiled for execution as discussed above with respect to FIG.2.

Accordingly, it should be appreciated that the apparatus and methoddisclosed above enable internal logic analyzers of each FPGA in acircuit design prototype to synchronously capture waveforms from thedevice when it is operating under the actual conditions that mightproduce a malfunction of the circuit design prototype in order to moreefficiently evaluate and debug the circuit design. It is also generallynoted that the above description and drawings are only to be consideredillustrative of specific embodiments, which achieve the features andadvantages described herein. Modifications and substitutions to specificprocess conditions can be made. Accordingly, the embodiments in thispatent document are not considered as being limited by the foregoingdescription and drawings.

What is claimed is:
 1. An apparatus for synchronizing triggers forwaveform capture of a circuit design in a prototyping system, theapparatus comprising: trigger net circuitry including at least one inputfor receiving a control signal and an output; and a plurality ofprogrammable logic devices each including: logic circuitry programmableto correspond to the circuit design; a logic analyzer circuit includingat least one logic connection coupled to the logic circuitry formonitoring signals of the circuit design; and a register having a datainput coupled to the output of the trigger net circuitry and an outputcoupled to a control input of the logic analyzer circuit, wherein one ofthe plurality of programmable logic devices is programmed to include thetrigger net circuitry.
 2. The apparatus of claim 1, wherein each of theplurality of programmable logic devices is a field-programmable gatearray.
 3. The apparatus of claim 1, wherein the trigger net circuitryincludes at least one multiplexer with a select input coupled to a hostinterface of the prototyping system.
 4. The apparatus of claim 3,wherein the host interface is configured to control the trigger netcircuitry to output a high logic signal.
 5. The apparatus of claim 1,wherein each register of the plurality of programmable logic devicessynchronously outputs a control logic signal to the respective logicanalyzer circuit coupled thereto.
 6. The apparatus of claim 5, whereineach logic analyzer circuit of the plurality of programmable logicdevices synchronously captures a waveform from the logic circuitry ofthe respective programmable logic device via the at least one logicconnection.
 7. The apparatus of claim 1, wherein each logic analyzercircuit of the plurality of programmable logic devices is programmed tosynchronously capture a waveform from the logic circuitry of therespective programmable logic device via the at least one logicconnection.
 8. A computer-implemented method for synchronizing triggersfor waveform capture of a prototyping system, the method comprising:partitioning a circuit design for programming into a plurality ofprogrammable logic devices; programming at least one of the plurality ofprogrammable logic devices to include trigger net circuitry, the triggernet circuitry including at least one trigger net and an output;programming an input of one register in each of the plurality ofprogrammable logic devices to receive a control signal from the outputof the trigger net circuitry; and programming an output of the oneregister in each of the plurality of programmable logic devices totransmit a trigger signal to a logic analyzer circuit in the respectiveprogrammable logic device.
 9. The computer-implemented method accordingto claim 8, further comprising programming at least one logic connectionof each logic analyzer circuit to receive at least one signal from logiccircuitry of the respective programmable logic device.
 10. Thecomputer-implemented method according to claim 9, further comprisingconnecting a host interface of the prototyping system to an input of thetrigger net circuitry.
 11. The computer-implemented method according toclaim 10, transmitting a control signal on the host interface to thetrigger net circuitry to potentially output a high logic signal based onthe logic programmed into the FPGA.
 12. The computer-implemented methodaccording to claim 11, further comprising synchronously outputting acontrol logic signal by each register of the plurality of programmablelogic devices to the respective logic analyzer circuit coupled thereto.13. The computer-implemented method according to claim 12, furthercomprising synchronously capturing, by each respective logic analyzercircuit, a waveform from the logic circuitry of the respectiveprogrammable logic device.
 14. A computer-readable non-transitorystorage medium having stored thereon a plurality of instructions, theplurality of instructions when executed by a computer, cause thecomputer to: partition a circuit design for programming into a pluralityof programmable logic devices; program at least one of the plurality ofprogrammable logic devices to include trigger net circuitry, the triggernet circuitry including at least one trigger net and an output; programan input of one register in each of the plurality of programmable logicdevices to receive a control signal from the output of the trigger netcircuitry; and program an output of the one register in each of theplurality of programmable logic devices to transmit a trigger signal toa logic analyzer circuit in the respective programmable logic device.15. The computer-readable non-transitory storage medium according toclaim 14, wherein the plurality of instructions when executed by acomputer further cause the computer to program at least one logicconnection of each logic analyzer circuit to receive at least oneoperating signal from logic circuitry of the respective programmablelogic device.
 16. The computer-readable non-transitory storage mediumaccording to claim 15, wherein the plurality of instructions whenexecuted by a computer further cause the computer to connect a hostinterface of the prototyping system to an input of the trigger netcircuitry.
 17. The computer-readable non-transitory storage mediumaccording to claim 16, wherein the plurality of instructions whenexecuted by a computer further cause the computer to transmit a controlsignal on the host interface to enable triggers and thereby potentiallyenable the trigger net circuitry to output a high logic signal.
 18. Thecomputer-readable non-transitory storage medium according to claim 17,wherein the plurality of instructions when executed by a computerfurther cause the computer to program each register of the plurality ofprogrammable logic devices to synchronously output a control logicsignal to the respective logic analyzer circuit coupled thereto.
 19. Thecomputer-readable non-transitory storage medium according to claim 16,wherein the plurality of instructions when executed by a computerfurther cause the computer to synchronously capture, by each respectivelogic analyzer circuit, a waveform from the logic circuitry of therespective programmable logic device.